The invention relates to a power semiconductor module in a plastic housing having surface-mountable flat external contacts and to a method for producing the same using a planar connecting technique on a metallic leadframe. In the case of such a power semiconductor module having surface-mountable flat external contacts, the external contact areas of the external contacts are arranged on the underside of the semiconductor module. Such a power semiconductor module has at least one power semiconductor chip, the top side of the power semiconductor chip having source contact areas and gate contact areas and the rear side of the semiconductor chip having a drain contact area.
Making contact with power semiconductor devices, in particular power semiconductor modules having a high current density in a plastic housing, is problematic owing to the high evolution of heat loss. This is because said heat loss has to be dissipated within the plastic housing via connections with the highest possible electrical and thermal conductivity from the contact areas of the semiconductor chip to corresponding connection contacts of a metallic leadframe.
One conventional connecting technique is wire contact-making. In this case, the connections are produced by means of bonding wires made of gold or aluminum, the contact between the bonding wires and the contact areas on the semiconductor chip and also the contact areas on a leadframe arising as a result of the metals involved being alloyed with energy being supplied. However, the relatively small cross-sectional areas of the wire connections are critical for a high connecting resistance. Moreover, such wire connections are an obstacle to further shrinking of the contact areas on the top side of the semiconductor chip, advancing chip miniaturization and increasing integration.
Further disadvantages of such bonding wire technologies are the thermomechanical loading on the semiconductor chip upon contact-making and the possible bonding wire drifting in the course of molding composition encapsulation of the module components in the course of embedding into a plastic housing composition. Furthermore, a further weak point for instances of bonding wires being torn away are the molten and subsequently recrystallized regions at the contact areas. Ageing processes of the alloy compounds are observed there, diffusion processes constituting a creeping increase in the contact resistance and hence a reliability problem for the power semiconductor module.
An alternative has been developed for P-TDSON housings (Plastic Thin Dual Small Outline Non leaded package). This alternative contact-making method is also known by the term “clamping clip method”, a metal clip instead of the bonding wires enabling large-area contact to be made with the source contact areas on account of its larger cross-sectional area, which leads to a reduction of the electrical resistance. At the same time, the clamping clip method improves the dissipation of heat from the chip top sides by virtue of a reduced thermal resistance and an increased heat buffer capacity of such a clamping clip connection. However, on account of its dimensions, the clip construction limits advancing and improved integration of power semiconductor chips in corresponding power semiconductor modules.
The flexibility of such clip structures is low with regard to the arrangement of the bonding contact areas, for which reason a change in each case necessitates a new clip construction. The contact-making on the contact areas of the semiconductor chip or on the contact pads of the “leadframe” is effected by soldering using a solder paste. The elimination of flux residues by means of a subsequent cleaning process forms a critical operation in this case. The flux residues have perfect adhesion on the components in the course of embedding and adversely influence the reliability of the power semiconductor module. In addition, fatigue cracks in the solder connections in the event of thermomechanical loading are a reliability problem.
The document WO 2004/077584 A2 discloses large-area metal coatings which are applied to an insulation layer of a substrate and in this case simultaneously produce the connection to contact areas on the top side of semiconductor chips. This technology requires, as the leadframe, a correspondingly prepared large-area substrate such as is known as a wiring substrate for BGA devices. Such prerequisites of a large-area plane substrate are not imposed, however, in the case of device housings such as the P-TDSON housing or P-VQFN housing (Plastic Very thin profile Quad Flat Non leaded package).
The document U.S. Pat. No. 5,637,922 also offers solutions with metal layers applied in large-area fashion and works on the basis of a conventional leadframe with flat conductors projecting laterally from the housing. Furthermore, the publication “Planar Metallization Interconnected 3-D Multichip Module” by Zhenxean Liang et al., 53. Electronic Compounds and Technology Conference 2003, pages 1090-1094, discloses orienting power semiconductor devices made of silicon with ceramic substrates in such a way that large-area metal coatings on the coplanar top side having ceramic substrate and semiconductor chip surface become possible without great disturbances. However, even this solution has the disadvantage that it is not very flexible and cannot readily be applied to power semiconductor modules having a plastic housing and having surface-mountable contacts such as the P-TDSON or the P-VQFN housings offer or have.
For these and other reasons, there is a need for the present invention.